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author | Robert Morris <[email protected]> | 2019-06-06 05:19:59 -0400 |
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committer | Robert Morris <[email protected]> | 2019-06-06 05:19:59 -0400 |
commit | 31ef85f55280b8cef6b71831ddffef1fb292c32e (patch) | |
tree | 2baf4628f17deb9fa6877d28e8f634e5310e3dea | |
parent | b05bcce93964fcf890c26567adf84cb83dbe5d37 (diff) | |
download | xv6-labs-31ef85f55280b8cef6b71831ddffef1fb292c32e.tar.gz xv6-labs-31ef85f55280b8cef6b71831ddffef1fb292c32e.tar.bz2 xv6-labs-31ef85f55280b8cef6b71831ddffef1fb292c32e.zip |
add plic.c
-rw-r--r-- | plic.c | 63 |
1 files changed, 63 insertions, 0 deletions
@@ -0,0 +1,63 @@ +#include "types.h" +#include "param.h" +#include "memlayout.h" +#include "riscv.h" +#include "defs.h" + +// +// the riscv Platform Level Interrupt Controller (PLIC). +// + +void +plicinit(void) +{ + // set uart's priority to be non-zero (otherwise disabled). + *(uint32*)(PLIC + UART0_IRQ*4) = 1; +} + +void +plicinithart(void) +{ + int hart = cpuid(); + + // set uart's enable bit for this hart's S-mode. + //*(uint32*)(PLIC + 0x2080)= (1 << UART0_IRQ); + *(uint32*)PLIC_SENABLE(hart)= (1 << UART0_IRQ); + + // set this hart's S-mode priority threshold to 0. + //*(uint32*)(PLIC + 0x201000) = 0; + *(uint32*)PLIC_SPRIORITY(hart) = 0; +} + +// return a bitmap of which IRQs are waiting +// to be served. +uint64 +plic_pending(void) +{ + uint64 mask; + + //mask = *(uint32*)(PLIC + 0x1000); + //mask |= (uint64)*(uint32*)(PLIC + 0x1004) << 32; + mask = *(uint64*)PLIC_PENDING; + + return mask; +} + +// ask the PLIC what interrupt we should serve. +int +plic_claim(void) +{ + int hart = cpuid(); + //int irq = *(uint32*)(PLIC + 0x201004); + int irq = *(uint32*)PLIC_SCLAIM(hart); + return irq; +} + +// tell the PLIC we've served this IRQ. +void +plic_complete(int irq) +{ + int hart = cpuid(); + //*(uint32*)(PLIC + 0x201004) = irq; + *(uint32*)PLIC_SCLAIM(hart) = irq; +} |