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| author | Robert Morris <[email protected]> | 2022-08-09 13:41:45 -0400 |
|---|---|---|
| committer | Robert Morris <[email protected]> | 2022-08-09 13:41:45 -0400 |
| commit | 3abd7a16dd6a0a529b7eab1ef31a3819b54a931e (patch) | |
| tree | f5be5470ac990bef28ae96d7e38902a502feedac | |
| parent | 9fc9f755e1f9ec56a452b334f6112028e0ec0329 (diff) | |
| download | xv6-labs-3abd7a16dd6a0a529b7eab1ef31a3819b54a931e.tar.gz xv6-labs-3abd7a16dd6a0a529b7eab1ef31a3819b54a931e.tar.bz2 xv6-labs-3abd7a16dd6a0a529b7eab1ef31a3819b54a931e.zip | |
comment
| -rw-r--r-- | kernel/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index 1f8a503..7e358f1 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -183,6 +183,7 @@ w_mtvec(uint64 x) asm volatile("csrw mtvec, %0" : : "r" (x)); } +// Physical Memory Protection static inline void w_pmpcfg0(uint64 x) { |