diff options
| author | rsc <rsc> | 2007-10-01 20:43:15 +0000 |
|---|---|---|
| committer | rsc <rsc> | 2007-10-01 20:43:15 +0000 |
| commit | 943fd378a1324ca60da72b271769fea4a86e36cb (patch) | |
| tree | a2510dc65a996e7d7fc49ab1e594ccb5a45f20ba /TRICKS | |
| parent | 9fd9f80431ad85552c0969831a3ccc3e800ac464 (diff) | |
| download | xv6-labs-943fd378a1324ca60da72b271769fea4a86e36cb.tar.gz xv6-labs-943fd378a1324ca60da72b271769fea4a86e36cb.tar.bz2 xv6-labs-943fd378a1324ca60da72b271769fea4a86e36cb.zip | |
Incorporate new understanding of/with Intel SMP spec.
Dropped cmpxchg in favor of xchg, to match lecture notes.
Use xchg to release lock, for future protection and to
keep gcc from acting clever.
Diffstat (limited to 'TRICKS')
| -rw-r--r-- | TRICKS | 8 |
1 files changed, 7 insertions, 1 deletions
@@ -102,5 +102,11 @@ after observing the earlier writes by CPU0. So any reads in B are guaranteed to observe the effects of writes in A. -Not sure about the second one yet. +According to the Intel manual behavior spec, the +second condition requires a serialization instruction +in release, to avoid reads in A happening after giving +up lk. No Intel SMP processor in existence actually +moves reads down after writes, but the language in +the spec allows it. There is no telling whether future +processors will need it. |