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| author | Robert Morris <[email protected]> | 2022-08-09 11:44:02 -0400 |
|---|---|---|
| committer | Robert Morris <[email protected]> | 2022-08-09 11:44:02 -0400 |
| commit | 9fc9f755e1f9ec56a452b334f6112028e0ec0329 (patch) | |
| tree | 5bc1ab85b436fde1bd4f6d72ed9c577919b92141 /kernel/riscv.h | |
| parent | ca6fc549341d30730247792b87edceacf1613834 (diff) | |
| download | xv6-labs-9fc9f755e1f9ec56a452b334f6112028e0ec0329.tar.gz xv6-labs-9fc9f755e1f9ec56a452b334f6112028e0ec0329.tar.bz2 xv6-labs-9fc9f755e1f9ec56a452b334f6112028e0ec0329.zip | |
adopt github PR98 (No need to store TRAPFRAME in sscratch register)
Diffstat (limited to 'kernel/riscv.h')
| -rw-r--r-- | kernel/riscv.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index 1691faf..1f8a503 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -1,3 +1,5 @@ +#ifndef __ASSEMBLER__ + // which hart (core) is this? static inline uint64 r_mhartid() @@ -331,6 +333,10 @@ sfence_vma() asm volatile("sfence.vma zero, zero"); } +typedef uint64 pte_t; +typedef uint64 *pagetable_t; // 512 PTEs + +#endif // __ASSEMBLER__ #define PGSIZE 4096 // bytes per page #define PGSHIFT 12 // bits of offset within a page @@ -361,6 +367,3 @@ sfence_vma() // Sv39, to avoid having to sign-extend virtual addresses // that have the high bit set. #define MAXVA (1L << (9 + 9 + 9 + 12 - 1)) - -typedef uint64 pte_t; -typedef uint64 *pagetable_t; // 512 PTEs |