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AgeCommit message (Collapse)AuthorFilesLines
2019-08-03alarm stuffRobert Morris1-69/+57
2019-08-02two notesFrans Kaashoek1-2/+7
2019-08-02Add simple crash recovery assignment to fs labFrans Kaashoek1-109/+215
2019-08-02nitsRobert Morris1-17/+15
2019-08-02some XXX questionsRobert Morris1-4/+23
2019-08-02oops, back to alarm()Robert Morris1-3/+3
2019-08-02Merge branch 'riscv' of g.csail.mit.edu:xv6-dev into riscvRobert Morris1-0/+171
2019-08-02sigalarmRobert Morris1-6/+7
2019-08-02Combine the linux mmap hw with memory-mapped files in xv6 into a separate labFrans Kaashoek1-0/+171
2019-08-02syscall lab nitsRobert Morris3-25/+25
2019-08-02Add uthreadFrans Kaashoek1-53/+216
2019-08-01xFrans Kaashoek2-6/+16
2019-08-01Merge branch 'riscv-bcache' into riscvFrans Kaashoek6-38/+68
2019-08-01fences for startingRobert Morris1-0/+2
2019-08-01First draft of text for mmap assignment.Frans Kaashoek1-1/+105
2019-07-30cut ramdiskRobert Morris1-3/+0
2019-07-30Import big file assignment.Frans Kaashoek1-0/+145
2019-07-30xFrans Kaashoek1-2/+16
2019-07-30Track in buf if disk "owns" bufferFrans Kaashoek2-3/+5
2019-07-30An easier version of bcache assignmentFrans Kaashoek1-7/+11
2019-07-30Make pin/unpin explicitFrans Kaashoek3-2/+20
2019-07-30The driver should free descriptors, not interrupt handler. ThisFrans Kaashoek1-3/+3
avoids handler freeing descriptors before driver sees that the request has completed.
2019-07-29Remove B_DIRTYFrans Kaashoek5-27/+19
Use refcnt to pin blocks into the cache Replace flags/B_VALID with a boolean field valid Use info[id].status to signal completion of disk interrupt Pass a read/write flag to virtio_disk_rw
2019-07-29checkpointFrans Kaashoek1-5/+40
2019-07-29Merge branch 'riscv' of g.csail.mit.edu:xv6-dev into riscvFrans Kaashoek2-12/+27
2019-07-28separate out timer init code for clarityRobert Morris1-10/+24
2019-07-28xxxRobert Morris1-2/+3
2019-07-28Merge branch 'riscv' of g.csail.mit.edu:xv6-dev into riscvFrans Kaashoek3-26/+11
2019-07-28Merge branch 'riscv' of g.csail.mit.edu:xv6-dev into riscvRobert Morris2-1/+91
2019-07-28argptr no longer needed, since copyin checksRobert Morris3-26/+11
2019-07-27a thoughtFrans Kaashoek1-0/+9
2019-07-27a bit moreFrans Kaashoek1-1/+6
2019-07-27Checkpoint start of locking labFrans Kaashoek2-1/+86
2019-07-27cleaner UART register interfaceRobert Morris2-26/+40
2019-07-27console/uart tweaksRobert Morris3-7/+20
2019-07-27beautify console.cRobert Morris3-35/+68
2019-07-27split printf into a separate file, to make console.c more like a driverRobert Morris5-134/+168
2019-07-26Pass over lab textFrans Kaashoek1-50/+60
2019-07-26fetchint isn't used any moreRobert Morris2-14/+0
2019-07-26???Robert Morris2-3/+4
2019-07-26Checkpoint: split alarmtest exercise in two exercisesFrans Kaashoek1-28/+144
2019-07-26machinevec -> timervecRobert Morris5-25/+26
2019-07-26uservec before userret in trampoline, to match book and kernelvecRobert Morris3-63/+69
2019-07-26Merge branch 'riscv' of g.csail.mit.edu:xv6-dev into riscvRobert Morris3-9/+249
2019-07-26trampin -> uservecRobert Morris6-17/+18
trampout -> userret
2019-07-25syscall lab/alarmFrans Kaashoek1-0/+196
2019-07-25Checkpoint start syscall labFrans Kaashoek1-35/+0
2019-07-25Add syscall tracing to the first xv6 labFrans Kaashoek1-5/+46
2019-07-25xFrans Kaashoek1-1/+1
2019-07-25a few name changes in panic msgFrans Kaashoek1-3/+3
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