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| author | Robert Morris <[email protected]> | 2019-06-05 11:42:03 -0400 |
|---|---|---|
| committer | Robert Morris <[email protected]> | 2019-06-05 11:42:03 -0400 |
| commit | f1a727b971a59bab6025b4c4111342c27356ca40 (patch) | |
| tree | d22d52c613bfc003e6fb75b5d137aeff9d954201 /.gdbinit.tmpl-riscv | |
| parent | ec3d3a1fceee437c640f9c5c05fc517edfb1899e (diff) | |
| download | xv6-labs-f1a727b971a59bab6025b4c4111342c27356ca40.tar.gz xv6-labs-f1a727b971a59bab6025b4c4111342c27356ca40.tar.bz2 xv6-labs-f1a727b971a59bab6025b4c4111342c27356ca40.zip | |
start at support for multiple CPUs
Diffstat (limited to '.gdbinit.tmpl-riscv')
| -rw-r--r-- | .gdbinit.tmpl-riscv | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/.gdbinit.tmpl-riscv b/.gdbinit.tmpl-riscv index 6ea36e1..c1616b6 100644 --- a/.gdbinit.tmpl-riscv +++ b/.gdbinit.tmpl-riscv @@ -1,3 +1,4 @@ +set confirm off set architecture riscv target remote 127.0.0.1:1234 symbol-file kernel |