summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorFrans Kaashoek <[email protected]>2019-07-29 11:44:55 -0400
committerFrans Kaashoek <[email protected]>2019-07-29 11:44:55 -0400
commit005773c0c3cf3119273d1fd001c01241f7eae5c2 (patch)
tree60605ba7f84b8556edd969135b5962f482cbea81
parent33494edad5970586ed61efc967405b07db529b72 (diff)
parent47b9cfee4991a74bb999b795e57d9c86b7f45c50 (diff)
downloadxv6-labs-005773c0c3cf3119273d1fd001c01241f7eae5c2.tar.gz
xv6-labs-005773c0c3cf3119273d1fd001c01241f7eae5c2.tar.bz2
xv6-labs-005773c0c3cf3119273d1fd001c01241f7eae5c2.zip
Merge branch 'riscv' of g.csail.mit.edu:xv6-dev into riscv
-rw-r--r--kernel/start.c34
-rw-r--r--kernel/uart.c5
2 files changed, 27 insertions, 12 deletions
diff --git a/kernel/start.c b/kernel/start.c
index 0f3453d..203c5e6 100644
--- a/kernel/start.c
+++ b/kernel/start.c
@@ -5,6 +5,7 @@
#include "defs.h"
void main();
+void timerinit();
// entry.S needs one stack per CPU.
__attribute__ ((aligned (16))) char stack0[4096 * NCPU];
@@ -36,15 +37,31 @@ start()
w_medeleg(0xffff);
w_mideleg(0xffff);
+ // ask for clock interrupts.
+ timerinit();
+
+ // keep each CPU's hartid in its tp register, for cpuid().
+ int id = r_mhartid();
+ w_tp(id);
+
+ // switch to supervisor mode and jump to main().
+ asm volatile("mret");
+}
+
+// set up to receive timer interrupts in machine mode,
+// which arrive at timervec in kernelvec.S,
+// which turns them into software interrupts for
+// devintr() in trap.c.
+void
+timerinit()
+{
+ // each CPU has a separate source of timer interrupts.
int id = r_mhartid();
- // set up to receive timer interrupts in machine mode,
- // which arrive at timervec in kernelvec.S,
- // which turns them into software interrupts for
- // devintr() in trap.c.
// ask the CLINT for a timer interrupt.
int interval = 1000000; // cycles; about 1/10th second in qemu.
*(uint64*)CLINT_MTIMECMP(id) = *(uint64*)CLINT_MTIME + interval;
+
// prepare information in scratch[] for timervec.
// scratch[0..3] : space for timervec to save registers.
// scratch[4] : address of CLINT MTIMECMP register.
@@ -53,16 +70,13 @@ start()
scratch[4] = CLINT_MTIMECMP(id);
scratch[5] = interval;
w_mscratch((uint64)scratch);
+
// set the machine-mode trap handler.
w_mtvec((uint64)timervec);
+
// enable machine-mode interrupts.
w_mstatus(r_mstatus() | MSTATUS_MIE);
+
// enable machine-mode timer interrupts.
w_mie(r_mie() | MIE_MTIE);
-
- // keep each CPU's hartid in its tp register, for cpuid().
- w_tp(id);
-
- // switch to supervisor mode and jump to main().
- asm volatile("mret");
}
diff --git a/kernel/uart.c b/kernel/uart.c
index 852a085..3a5cdc4 100644
--- a/kernel/uart.c
+++ b/kernel/uart.c
@@ -15,8 +15,9 @@
// address of one of the registers.
#define Reg(reg) ((volatile unsigned char *)(UART0 + reg))
-// the registers. some have different meanings for
-// read and write.
+// the UART control registers.
+// some have different meanings for
+// read vs write.
// http://byterunner.com/16550.html
#define RHR 0 // receive holding register (for input bytes)
#define THR 0 // transmit holding register (for output bytes)