diff options
author | Russ Cox <[email protected]> | 2009-07-11 19:24:56 -0700 |
---|---|---|
committer | Russ Cox <[email protected]> | 2009-07-11 19:24:56 -0700 |
commit | 2de1c550cab8a5812dc9965313fce00816a003eb (patch) | |
tree | 6ed2412d4f47546a1ee9fa2fe3be4b09cf9ac5eb | |
parent | 887f19686cf377db55953dac651ca8147c268092 (diff) | |
download | xv6-labs-2de1c550cab8a5812dc9965313fce00816a003eb.tar.gz xv6-labs-2de1c550cab8a5812dc9965313fce00816a003eb.tar.bz2 xv6-labs-2de1c550cab8a5812dc9965313fce00816a003eb.zip |
trap cleanup
IRQ_OFFSET -> T_IRQ0 (a trap number not an IRQ number)
T_SYSCALL 0x30 -> 0x40 (move out of IRQ range)
-rw-r--r-- | ioapic.c | 4 | ||||
-rw-r--r-- | lapic.c | 6 | ||||
-rw-r--r-- | picirq.c | 4 |
3 files changed, 7 insertions, 7 deletions
@@ -62,7 +62,7 @@ ioapicinit(void) // Mark all interrupts edge-triggered, active high, disabled, // and not routed to any CPUs. for(i = 0; i <= maxintr; i++){ - ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (IRQ_OFFSET + i)); + ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (T_IRQ0 + i)); ioapicwrite(REG_TABLE+2*i+1, 0); } } @@ -76,6 +76,6 @@ ioapicenable(int irq, int cpunum) // Mark interrupt edge-triggered, active high, // enabled, and routed to the given cpunum, // which happens to be that cpu's APIC ID. - ioapicwrite(REG_TABLE+2*irq, IRQ_OFFSET + irq); + ioapicwrite(REG_TABLE+2*irq, T_IRQ0 + irq); ioapicwrite(REG_TABLE+2*irq+1, cpunum << 24); } @@ -52,14 +52,14 @@ lapicinit(int c) return; // Enable local APIC; set spurious interrupt vector. - lapicw(SVR, ENABLE | (IRQ_OFFSET+IRQ_SPURIOUS)); + lapicw(SVR, ENABLE | (T_IRQ0 + IRQ_SPURIOUS)); // The timer repeatedly counts down at bus frequency // from lapic[TICR] and then issues an interrupt. // If xv6 cared more about precise timekeeping, // TICR would be calibrated using an external time source. lapicw(TDCR, X1); - lapicw(TIMER, PERIODIC | (IRQ_OFFSET + IRQ_TIMER)); + lapicw(TIMER, PERIODIC | (T_IRQ0 + IRQ_TIMER)); lapicw(TICR, 10000000); // Disable logical interrupt lines. @@ -72,7 +72,7 @@ lapicinit(int c) lapicw(PCINT, MASKED); // Map error interrupt to IRQ_ERROR. - lapicw(ERROR, IRQ_OFFSET+IRQ_ERROR); + lapicw(ERROR, T_IRQ0 + IRQ_ERROR); // Clear error status register (requires back-to-back writes). lapicw(ESR, 0); @@ -45,7 +45,7 @@ picinit(void) outb(IO_PIC1, 0x11); // ICW2: Vector offset - outb(IO_PIC1+1, IRQ_OFFSET); + outb(IO_PIC1+1, T_IRQ0); // ICW3: (master PIC) bit mask of IR lines connected to slaves // (slave PIC) 3-bit # of slave's connection to master @@ -63,7 +63,7 @@ picinit(void) // Set up slave (8259A-2) outb(IO_PIC2, 0x11); // ICW1 - outb(IO_PIC2+1, IRQ_OFFSET + 8); // ICW2 + outb(IO_PIC2+1, T_IRQ0 + 8); // ICW2 outb(IO_PIC2+1, IRQ_SLAVE); // ICW3 // NB Automatic EOI mode doesn't tend to work on the slave. // Linux source code says it's "to be investigated". |