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| author | Matt Harvey <[email protected]> | 2020-09-14 14:49:57 -0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2020-09-14 14:49:57 -0700 |
| commit | 6781ac00366e2c46c0a4ed18dfd60e41a3fa4ae6 (patch) | |
| tree | 942fd44b1f9d20de7ee8cbf473470874bf43f03c | |
| parent | 79899c747970f7b7e1cd69f714e2146621727bc5 (diff) | |
| download | xv6-labs-6781ac00366e2c46c0a4ed18dfd60e41a3fa4ae6.tar.gz xv6-labs-6781ac00366e2c46c0a4ed18dfd60e41a3fa4ae6.tar.bz2 xv6-labs-6781ac00366e2c46c0a4ed18dfd60e41a3fa4ae6.zip | |
Corrects order of UART RX/TX interrupt enable bits
(per http://byterunner.com/16550.html and manually tested in qemu bare metal echo)
| -rw-r--r-- | kernel/uart.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/uart.c b/kernel/uart.c index ce89615..d586ea4 100644 --- a/kernel/uart.c +++ b/kernel/uart.c @@ -22,8 +22,8 @@ #define RHR 0 // receive holding register (for input bytes) #define THR 0 // transmit holding register (for output bytes) #define IER 1 // interrupt enable register -#define IER_TX_ENABLE (1<<0) -#define IER_RX_ENABLE (1<<1) +#define IER_RX_ENABLE (1<<0) +#define IER_TX_ENABLE (1<<1) #define FCR 2 // FIFO control register #define FCR_FIFO_ENABLE (1<<0) #define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs |