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authorRobert Morris <[email protected]>2019-06-03 14:16:51 -0400
committerRobert Morris <[email protected]>2019-06-03 14:16:51 -0400
commite630e0743b8c1a0f9ebca702811bd59065c9f457 (patch)
tree771a16bcc90377f2e3bf696f4fa887de95848ec4
parenta9c1a6f742886a9d45e5c625cf4f9b1b5c7a8cc4 (diff)
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-rw-r--r--trap.c24
1 files changed, 13 insertions, 11 deletions
diff --git a/trap.c b/trap.c
index 2b8fd41..9fe3c85 100644
--- a/trap.c
+++ b/trap.c
@@ -21,6 +21,19 @@ trapinit(void)
// send interrupts and exceptions to kerneltrap().
w_stvec((uint64)kerneltrap);
+ // set up the riscv Platform Level Interrupt Controller
+ // to send uart interrupts to hart 0 S-Mode.
+
+ // qemu makes UART0 be interrupt number 10.
+ int irq = 10;
+ // set uart's priority to be non-zero (otherwise disabled).
+ *(uint*)(0x0c000000L + irq*4) = 1;
+ // set uart's enable bit for hart 0 S-mode.
+ *(uint*)0x0c002080 = (1 << irq);
+
+ // set hart 0 S-mode priority threshold to 0.
+ *(uint*)0x0c201000 = 0;
+
initlock(&tickslock, "time");
}
@@ -43,17 +56,6 @@ usertrap(void)
// save user program counter.
p->tf->epc = r_sepc();
- // PLIC setup
- // qemu makes UART0 be interrupt number 10.
- int irq = 10;
- // set uart's priority to be non-zero (otherwise disabled).
- *(uint*)(0x0c000000L + irq*4) = 1;
- // set uart's enable bit for hart 0 s-mode.
- *(uint*)0x0c002080 = (1 << irq);
-
- // hart 0 S-mode priority threshold.
- *(uint*)0x0c201000 = 0;
-
intr_on();
if(r_scause() == 8){