diff options
author | kaashoek <kaashoek> | 2006-09-08 15:07:45 +0000 |
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committer | kaashoek <kaashoek> | 2006-09-08 15:07:45 +0000 |
commit | 5c596bb3a7b3e08760ac5c033680c9957e4e2842 (patch) | |
tree | 29dc342b35dcf1905168141d26ef532d37577072 | |
parent | 5cb7877e0f1dd09a513859f018d3981a9c9d17ad (diff) | |
download | xv6-labs-5c596bb3a7b3e08760ac5c033680c9957e4e2842.tar.gz xv6-labs-5c596bb3a7b3e08760ac5c033680c9957e4e2842.tar.bz2 xv6-labs-5c596bb3a7b3e08760ac5c033680c9957e4e2842.zip |
consistency.
-rw-r--r-- | ioapic.c | 70 | ||||
-rw-r--r-- | lapic.c | 17 |
2 files changed, 45 insertions, 42 deletions
@@ -37,30 +37,31 @@ ioapic_init(void) uchar id; int i; - if (ismp) { - io = (struct ioapic*) IO_APIC_BASE; - l = ioapic_read(io, IOAPIC_VER); - nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1; - id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT; - if(id != ioapic_id) - cprintf("ioapic_init: id isn't equal to ioapic_id; not a MP\n"); - for(i = 0; i < nintr; i++) { - // active-hi and edge-triggered for ISA interrupts - // Assume that pin 0 on the first I/O APIC is an ExtINT pin. - // Assume that pins 1-15 are ISA interrupts - l = ioapic_read(io, IOAPIC_REDTBL_LO(i)); - l = l & ~IOART_INTMASK; // allow INTs - l |= IOART_INTMSET; - l = l & ~IOART_INTPOL; // active hi - l = l & ~IOART_TRGRMOD; // edgee triggered - l = l & ~IOART_DELMOD; // fixed - l = l & ~IOART_DESTMOD; // physical mode - l = l | (IRQ_OFFSET + i); // vector - ioapic_write(io, IOAPIC_REDTBL_LO(i), l); - h = ioapic_read(io, IOAPIC_REDTBL_HI(i)); - h &= ~IOART_DEST; - ioapic_write(io, IOAPIC_REDTBL_HI(i), h); - } + if (!ismp) + return; + + io = (struct ioapic*) IO_APIC_BASE; + l = ioapic_read(io, IOAPIC_VER); + nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1; + id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT; + if(id != ioapic_id) + cprintf("ioapic_init: id isn't equal to ioapic_id; not a MP\n"); + for(i = 0; i < nintr; i++) { + // active-hi and edge-triggered for ISA interrupts + // Assume that pin 0 on the first I/O APIC is an ExtINT pin. + // Assume that pins 1-15 are ISA interrupts + l = ioapic_read(io, IOAPIC_REDTBL_LO(i)); + l = l & ~IOART_INTMASK; // allow INTs + l |= IOART_INTMSET; + l = l & ~IOART_INTPOL; // active hi + l = l & ~IOART_TRGRMOD; // edgee triggered + l = l & ~IOART_DELMOD; // fixed + l = l & ~IOART_DESTMOD; // physical mode + l = l | (IRQ_OFFSET + i); // vector + ioapic_write(io, IOAPIC_REDTBL_LO(i), l); + h = ioapic_read(io, IOAPIC_REDTBL_HI(i)); + h &= ~IOART_DEST; + ioapic_write(io, IOAPIC_REDTBL_HI(i), h); } } @@ -70,14 +71,15 @@ ioapic_enable (int irq, int cpunum) uint l, h; struct ioapic *io; - if (ismp) { - io = (struct ioapic*) IO_APIC_BASE; - l = ioapic_read(io, IOAPIC_REDTBL_LO(irq)); - l = l & ~IOART_INTMASK; // allow INTs - ioapic_write(io, IOAPIC_REDTBL_LO(irq), l); - h = ioapic_read(io, IOAPIC_REDTBL_HI(irq)); - h &= ~IOART_DEST; - h |= (cpunum << APIC_ID_SHIFT); - ioapic_write(io, IOAPIC_REDTBL_HI(irq), h); - } + if (!ismp) + return; + + io = (struct ioapic*) IO_APIC_BASE; + l = ioapic_read(io, IOAPIC_REDTBL_LO(irq)); + l = l & ~IOART_INTMASK; // allow INTs + ioapic_write(io, IOAPIC_REDTBL_LO(irq), l); + h = ioapic_read(io, IOAPIC_REDTBL_HI(irq)); + h &= ~IOART_DEST; + h |= (cpunum << APIC_ID_SHIFT); + ioapic_write(io, IOAPIC_REDTBL_HI(irq), h); } @@ -105,13 +105,14 @@ lapic_write(int r, int data) void lapic_timerinit(void) { - if (lapicaddr) { - lapic_write(LAPIC_TDCR, LAPIC_X1); - lapic_write(LAPIC_TIMER, LAPIC_CLKIN | LAPIC_PERIODIC | - (IRQ_OFFSET + IRQ_TIMER)); - lapic_write(LAPIC_TCCR, 10000000); - lapic_write(LAPIC_TICR, 10000000); - } + if (!lapicaddr) + return; + + lapic_write(LAPIC_TDCR, LAPIC_X1); + lapic_write(LAPIC_TIMER, LAPIC_CLKIN | LAPIC_PERIODIC | + (IRQ_OFFSET + IRQ_TIMER)); + lapic_write(LAPIC_TCCR, 10000000); + lapic_write(LAPIC_TICR, 10000000); } void @@ -126,7 +127,7 @@ lapic_init(int c) { uint r, lvt; - if (lapicaddr == 0) + if (!lapicaddr) return; lapic_write(LAPIC_DFR, 0xFFFFFFFF); // Set dst format register |