Apparently the initial interrupt count lapic[TICR]

must be set *after* initializing the lapic[TIMER] vector.

Doing this, we now get clock interrupts on cpu 1.
(No idea why we always got them on cpu 0.)

Don't write to TCCR - it is read-only.

2 files changed, 3 insertions, 10 deletions

diff --git a/defs.h b/defs.h
index 7540e1e..b9e0e98 100644
--- a/defs.h
+++ b/defs.h
@@ -70,13 +70,9 @@ void            kbd_intr(void);
 // lapic.c
 int             cpu(void);
 extern volatile uint*    lapic;
-void            lapic_disableintr(void);
-void            lapic_enableintr(void);
 void            lapic_eoi(void);
 void            lapic_init(int);
 void            lapic_startap(uchar, uint);
-void            lapic_timerinit(void);
-void            lapic_timerintr(void);
 
 // mp.c
 extern int      ismp;
diff --git a/lapic.c b/lapic.c
index 5df4f86..2bf97fb 100644
--- a/lapic.c
+++ b/lapic.c
@@ -46,14 +46,11 @@ lapic_init(int c)
 
   // The timer repeatedly counts down at bus frequency
   // from lapic[TICR] and then issues an interrupt.  
-  // Lapic[TCCR] is the current counter value.
-  // If xv6 cared more about precise timekeeping, the
-  // values of TICR and TCCR would be calibrated using
-  // an external time source.
+  // If xv6 cared more about precise timekeeping,
+  // TICR would be calibrated using an external time source.
   lapic[TDCR] = X1;
-  lapic[TICR] = 10000000;
-  lapic[TCCR] = 10000000;
   lapic[TIMER] = PERIODIC | (IRQ_OFFSET + IRQ_TIMER);
+  lapic[TICR] = 10000000; 
 
   // Disable logical interrupt lines.
   lapic[LINT0] = MASKED;