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| author | Robert Morris <rtm@csail.mit.edu> | 2019-06-06 05:19:35 -0400 |
|---|---|---|
| committer | Robert Morris <rtm@csail.mit.edu> | 2019-06-06 05:19:35 -0400 |
| commit | b05bcce93964fcf890c26567adf84cb83dbe5d37 (patch) | |
| tree | 2149b331229fa121218829fe4f7de434f7fe5905 | |
| parent | dff7ab3f8f969cb9c1e95e6d7a74b99428e06971 (diff) | |
| download | xv6-labs-b05bcce93964fcf890c26567adf84cb83dbe5d37.tar.gz xv6-labs-b05bcce93964fcf890c26567adf84cb83dbe5d37.tar.bz2 xv6-labs-b05bcce93964fcf890c26567adf84cb83dbe5d37.zip | |
add kernelvec
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | kernelvec.S | 112 |
2 files changed, 113 insertions, 1 deletions
@@ -153,7 +153,7 @@ QEMUGDB = $(shell if $(QEMU) -help | grep -q '^-gdb'; \ then echo "-gdb tcp::$(GDBPORT)"; \ else echo "-s -p $(GDBPORT)"; fi) ifndef CPUS -CPUS := 2 +CPUS := 1 endif QEMUOPTS = -machine virt -kernel kernel -m 3G -smp $(CPUS) -nographic QEMUOPTS += -initrd fs.img diff --git a/kernelvec.S b/kernelvec.S new file mode 100644 index 0000000..4f52688 --- /dev/null +++ b/kernelvec.S @@ -0,0 +1,112 @@ + # + # interrupts and exceptions while in supervisor + # mode come here. + # + # push all registers, call kerneltrap(), restore, return. + # +.globl kerneltrap +.globl kernelvec +.align 4 +kernelvec: + addi sp, sp, -256 + + sd ra, 0(sp) + sd sp, 8(sp) + sd gp, 16(sp) + sd tp, 24(sp) + sd t0, 32(sp) + sd t1, 40(sp) + sd t2, 48(sp) + sd s0, 56(sp) + sd s1, 64(sp) + sd a0, 72(sp) + sd a1, 80(sp) + sd a2, 88(sp) + sd a3, 96(sp) + sd a4, 104(sp) + sd a5, 112(sp) + sd a6, 120(sp) + sd a7, 128(sp) + sd s2, 136(sp) + sd s3, 144(sp) + sd s4, 152(sp) + sd s5, 160(sp) + sd s6, 168(sp) + sd s7, 176(sp) + sd s8, 184(sp) + sd s9, 192(sp) + sd s10, 200(sp) + sd s11, 208(sp) + sd t3, 216(sp) + sd t4, 224(sp) + sd t5, 232(sp) + sd t6, 240(sp) + + call kerneltrap + + ld ra, 0(sp) + ld sp, 8(sp) + ld gp, 16(sp) + ld tp, 24(sp) + ld t0, 32(sp) + ld t1, 40(sp) + ld t2, 48(sp) + ld s0, 56(sp) + ld s1, 64(sp) + ld a0, 72(sp) + ld a1, 80(sp) + ld a2, 88(sp) + ld a3, 96(sp) + ld a4, 104(sp) + ld a5, 112(sp) + ld a6, 120(sp) + ld a7, 128(sp) + ld s2, 136(sp) + ld s3, 144(sp) + ld s4, 152(sp) + ld s5, 160(sp) + ld s6, 168(sp) + ld s7, 176(sp) + ld s8, 184(sp) + ld s9, 192(sp) + ld s10, 200(sp) + ld s11, 208(sp) + ld t3, 216(sp) + ld t4, 224(sp) + ld t5, 232(sp) + ld t6, 240(sp) + + addi sp, sp, 256 + + sret + + # + # machine-mode timer interrupt. + # +.globl machinevec +.align 4 +machinevec: + csrrw a0, mscratch, a0 + sd a1, 0(a0) + sd a2, 8(a0) + sd a3, 16(a0) + sd a4, 24(a0) + + # add another second to mtimecmp0. + ld a1, 32(a0) # CLINT_MTIMECMP(hart) + ld a2, 40(a0) # ticks per second + ld a3, 0(a1) + add a3, a3, a2 + sd a3, 0(a1) + + # raise a supervisor software interrupt. + li a1, 2 + csrw sip, a1 + + ld a4, 24(a0) + ld a3, 16(a0) + ld a2, 8(a0) + ld a1, 0(a0) + csrrw a0, mscratch, a0 + + mret |