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| author | rsc <rsc> | 2007-12-20 18:27:07 +0000 |
|---|---|---|
| committer | rsc <rsc> | 2007-12-20 18:27:07 +0000 |
| commit | eadbd55af2b5d5a7e20f9b6803686ceed01f43ec (patch) | |
| tree | 574d92af0e79e9a74a5d2d60307f5415fca01f52 | |
| parent | c2258bf4d249c34f26a4ed3c2d6ced81744c654e (diff) | |
| download | xv6-labs-eadbd55af2b5d5a7e20f9b6803686ceed01f43ec.tar.gz xv6-labs-eadbd55af2b5d5a7e20f9b6803686ceed01f43ec.tar.bz2 xv6-labs-eadbd55af2b5d5a7e20f9b6803686ceed01f43ec.zip | |
oops - wrong bit (vic zandy)
| -rw-r--r-- | ioapic.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -17,7 +17,7 @@ // The first (low) register in a pair contains configuration bits. // The second (high) register contains a bitmask telling which // CPUs can serve that interrupt. -#define INT_DISABLED 0x00100000 // Interrupt disabled +#define INT_DISABLED 0x00010000 // Interrupt disabled #define INT_LEVEL 0x00008000 // Level-triggered (vs edge-) #define INT_ACTIVELOW 0x00002000 // Active low (vs high) #define INT_LOGICAL 0x00000800 // Destination is CPU id (vs APIC ID) |