diff options
| author | Russ Cox <rsc@swtch.com> | 2009-07-11 19:24:56 -0700 |
|---|---|---|
| committer | Russ Cox <rsc@swtch.com> | 2009-07-11 19:24:56 -0700 |
| commit | 2de1c550cab8a5812dc9965313fce00816a003eb (patch) | |
| tree | 6ed2412d4f47546a1ee9fa2fe3be4b09cf9ac5eb /ioapic.c | |
| parent | 887f19686cf377db55953dac651ca8147c268092 (diff) | |
| download | xv6-labs-2de1c550cab8a5812dc9965313fce00816a003eb.tar.gz xv6-labs-2de1c550cab8a5812dc9965313fce00816a003eb.tar.bz2 xv6-labs-2de1c550cab8a5812dc9965313fce00816a003eb.zip | |
trap cleanup
IRQ_OFFSET -> T_IRQ0 (a trap number not an IRQ number)
T_SYSCALL 0x30 -> 0x40 (move out of IRQ range)
Diffstat (limited to 'ioapic.c')
| -rw-r--r-- | ioapic.c | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -62,7 +62,7 @@ ioapicinit(void) // Mark all interrupts edge-triggered, active high, disabled, // and not routed to any CPUs. for(i = 0; i <= maxintr; i++){ - ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (IRQ_OFFSET + i)); + ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (T_IRQ0 + i)); ioapicwrite(REG_TABLE+2*i+1, 0); } } @@ -76,6 +76,6 @@ ioapicenable(int irq, int cpunum) // Mark interrupt edge-triggered, active high, // enabled, and routed to the given cpunum, // which happens to be that cpu's APIC ID. - ioapicwrite(REG_TABLE+2*irq, IRQ_OFFSET + irq); + ioapicwrite(REG_TABLE+2*irq, T_IRQ0 + irq); ioapicwrite(REG_TABLE+2*irq+1, cpunum << 24); } |