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| author | Robert Morris <rtm@csail.mit.edu> | 2020-10-05 15:28:01 -0400 |
|---|---|---|
| committer | Robert Morris <rtm@csail.mit.edu> | 2020-10-05 15:28:01 -0400 |
| commit | 6c167595037a0872338d999c7ce0971a5606dedb (patch) | |
| tree | e609ecbda6a195fae34e9150ac59f592947c408b /kernel/kernelvec.S | |
| parent | 0c55849d28a2df0416d28c83bc9da47411e2c78f (diff) | |
| download | xv6-labs-6c167595037a0872338d999c7ce0971a5606dedb.tar.gz xv6-labs-6c167595037a0872338d999c7ce0971a5606dedb.tar.bz2 xv6-labs-6c167595037a0872338d999c7ce0971a5606dedb.zip | |
more explicable scratch area size for machine-mode timer interrupts
Diffstat (limited to 'kernel/kernelvec.S')
| -rw-r--r-- | kernel/kernelvec.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/kernel/kernelvec.S b/kernel/kernelvec.S index 3e9d3e9..f42a364 100644 --- a/kernel/kernelvec.S +++ b/kernel/kernelvec.S @@ -93,8 +93,8 @@ kernelvec: timervec: # start.c has set up the memory that mscratch points to: # scratch[0,8,16] : register save area. - # scratch[32] : address of CLINT's MTIMECMP register. - # scratch[40] : desired interval between interrupts. + # scratch[24] : address of CLINT's MTIMECMP register. + # scratch[32] : desired interval between interrupts. csrrw a0, mscratch, a0 sd a1, 0(a0) @@ -103,8 +103,8 @@ timervec: # schedule the next timer interrupt # by adding interval to mtimecmp. - ld a1, 32(a0) # CLINT_MTIMECMP(hart) - ld a2, 40(a0) # interval + ld a1, 24(a0) # CLINT_MTIMECMP(hart) + ld a2, 32(a0) # interval ld a3, 0(a1) add a3, a3, a2 sd a3, 0(a1) |