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| author | Sanjit Bhat <[email protected]> | 2023-10-25 19:42:59 -0400 |
|---|---|---|
| committer | Sanjit Bhat <[email protected]> | 2023-10-25 19:42:59 -0400 |
| commit | 1ed40716eb54e371df9d1814b9129666b3fe4f09 (patch) | |
| tree | 84666aacb6d6a9554b09500c0b0420870af2e19e /kernel/plic.c | |
| parent | 74c1eba516fdb0ec1a17b16be7e76613ccba92bf (diff) | |
| download | xv6-labs-1ed40716eb54e371df9d1814b9129666b3fe4f09.tar.gz xv6-labs-1ed40716eb54e371df9d1814b9129666b3fe4f09.tar.bz2 xv6-labs-1ed40716eb54e371df9d1814b9129666b3fe4f09.zip | |
release lab net
Diffstat (limited to 'kernel/plic.c')
| -rw-r--r-- | kernel/plic.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/plic.c b/kernel/plic.c index 4175db9..5c9d96a 100644 --- a/kernel/plic.c +++ b/kernel/plic.c @@ -14,6 +14,13 @@ plicinit(void) // set desired IRQ priorities non-zero (otherwise disabled). *(uint32*)(PLIC + UART0_IRQ*4) = 1; *(uint32*)(PLIC + VIRTIO0_IRQ*4) = 1; + +#ifdef LAB_NET + // PCIE IRQs are 32 to 35 + for(int irq = 1; irq < 0x35; irq++){ + *(uint32*)(PLIC + irq*4) = 1; + } +#endif } void @@ -25,6 +32,11 @@ plicinithart(void) // for the uart and virtio disk. *(uint32*)PLIC_SENABLE(hart) = (1 << UART0_IRQ) | (1 << VIRTIO0_IRQ); +#ifdef LAB_NET + // hack to get at next 32 IRQs for e1000 + *(uint32*)(PLIC_SENABLE(hart)+4) = 0xffffffff; +#endif + // set this hart's S-mode priority threshold to 0. *(uint32*)PLIC_SPRIORITY(hart) = 0; } |