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author | Mole Shang <[email protected]> | 2024-02-14 20:46:23 +0800 |
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committer | Mole Shang <[email protected]> | 2024-02-14 20:46:23 +0800 |
commit | f98eeb30507040dc916b2a337818830954ee1d4a (patch) | |
tree | a741cb0bbd6be96d8084e72b4af895ac093a2b48 /kernel/plic.c | |
parent | 0de5ac779602f562a038e5ad27163d85bc71638b (diff) | |
parent | 904885a96efd1dd0221585f67477f5a39bcce7f7 (diff) | |
download | xv6-labs-f98eeb30507040dc916b2a337818830954ee1d4a.tar.gz xv6-labs-f98eeb30507040dc916b2a337818830954ee1d4a.tar.bz2 xv6-labs-f98eeb30507040dc916b2a337818830954ee1d4a.zip |
Merge branch 'net' into lock
Conflicts:
.gitignore
Makefile
conf/lab.mk
kernel/defs.h
user/user.h
Diffstat (limited to 'kernel/plic.c')
-rw-r--r-- | kernel/plic.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/plic.c b/kernel/plic.c index 4175db9..5c9d96a 100644 --- a/kernel/plic.c +++ b/kernel/plic.c @@ -14,6 +14,13 @@ plicinit(void) // set desired IRQ priorities non-zero (otherwise disabled). *(uint32*)(PLIC + UART0_IRQ*4) = 1; *(uint32*)(PLIC + VIRTIO0_IRQ*4) = 1; + +#ifdef LAB_NET + // PCIE IRQs are 32 to 35 + for(int irq = 1; irq < 0x35; irq++){ + *(uint32*)(PLIC + irq*4) = 1; + } +#endif } void @@ -25,6 +32,11 @@ plicinithart(void) // for the uart and virtio disk. *(uint32*)PLIC_SENABLE(hart) = (1 << UART0_IRQ) | (1 << VIRTIO0_IRQ); +#ifdef LAB_NET + // hack to get at next 32 IRQs for e1000 + *(uint32*)(PLIC_SENABLE(hart)+4) = 0xffffffff; +#endif + // set this hart's S-mode priority threshold to 0. *(uint32*)PLIC_SPRIORITY(hart) = 0; } |