diff options
| author | Robert Morris <[email protected]> | 2022-08-09 14:17:46 -0400 |
|---|---|---|
| committer | Robert Morris <[email protected]> | 2022-08-09 14:17:46 -0400 |
| commit | 27a669ef25c11e452bf2bbe01341adb36176ab73 (patch) | |
| tree | 0f478e5048d0600b5d0dec8c1eebcd5632e3a9a7 /kernel/riscv.h | |
| parent | af9abaca0543e392812fcde1138e68892b6c70bc (diff) | |
| download | xv6-labs-27a669ef25c11e452bf2bbe01341adb36176ab73.tar.gz xv6-labs-27a669ef25c11e452bf2bbe01341adb36176ab73.tar.bz2 xv6-labs-27a669ef25c11e452bf2bbe01341adb36176ab73.zip | |
comment nits
Diffstat (limited to 'kernel/riscv.h')
| -rw-r--r-- | kernel/riscv.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index 645a775..20a01db 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -295,7 +295,7 @@ r_sp() return x; } -// read and write tp, the thread pointer, which holds +// read and write tp, the thread pointer, which xv6 uses to hold // this core's hartid (core number), the index into cpus[]. static inline uint64 r_tp() @@ -342,7 +342,7 @@ typedef uint64 *pagetable_t; // 512 PTEs #define PTE_R (1L << 1) #define PTE_W (1L << 2) #define PTE_X (1L << 3) -#define PTE_U (1L << 4) // 1 -> user can access +#define PTE_U (1L << 4) // user can access // shift a physical address to the right place for a PTE. #define PA2PTE(pa) ((((uint64)pa) >> 12) << 10) |