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| author | Sanjit Bhat <[email protected]> | 2023-10-30 14:39:28 -0500 |
|---|---|---|
| committer | Sanjit Bhat <[email protected]> | 2023-10-30 14:39:28 -0500 |
| commit | 3808f903625f42f58aa95e43e3caca3efaa4d118 (patch) | |
| tree | ad8f5a0e376c246cb60c7cd0940517ea834e610e /kernel/riscv.h | |
| parent | 74c1eba516fdb0ec1a17b16be7e76613ccba92bf (diff) | |
| download | xv6-labs-3808f903625f42f58aa95e43e3caca3efaa4d118.tar.gz xv6-labs-3808f903625f42f58aa95e43e3caca3efaa4d118.tar.bz2 xv6-labs-3808f903625f42f58aa95e43e3caca3efaa4d118.zip | |
lock: release lab
Diffstat (limited to 'kernel/riscv.h')
| -rw-r--r-- | kernel/riscv.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index 20a01db..adc3e38 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -295,6 +295,14 @@ r_sp() return x; } +static inline uint64 +r_fp() +{ + uint64 x; + asm volatile("mv %0, s0" : "=r" (x) ); + return x; +} + // read and write tp, the thread pointer, which xv6 uses to hold // this core's hartid (core number), the index into cpus[]. static inline uint64 @@ -344,6 +352,9 @@ typedef uint64 *pagetable_t; // 512 PTEs #define PTE_X (1L << 3) #define PTE_U (1L << 4) // user can access + + + // shift a physical address to the right place for a PTE. #define PA2PTE(pa) ((((uint64)pa) >> 12) << 10) |