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| author | Robert Morris <[email protected]> | 2019-07-25 05:35:03 -0400 |
|---|---|---|
| committer | Robert Morris <[email protected]> | 2019-07-25 05:35:03 -0400 |
| commit | 5d5e4e065f4e593c9e396a52b8e599cdc62c9e7d (patch) | |
| tree | 0eaa24e2b0f489a65eae959c5f3b7b419a9ea214 /kernel/riscv.h | |
| parent | aef3e0f5a41c3b45eeb47e407cacb6cfa59168a0 (diff) | |
| download | xv6-labs-5d5e4e065f4e593c9e396a52b8e599cdc62c9e7d.tar.gz xv6-labs-5d5e4e065f4e593c9e396a52b8e599cdc62c9e7d.tar.bz2 xv6-labs-5d5e4e065f4e593c9e396a52b8e599cdc62c9e7d.zip | |
comments for timer setup
Diffstat (limited to 'kernel/riscv.h')
| -rw-r--r-- | kernel/riscv.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index e35f3bc..63f71b4 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -9,11 +9,11 @@ r_mhartid() // Machine Status Register, mstatus -#define MSTATUS_MPP_MASK (3L << 11) +#define MSTATUS_MPP_MASK (3L << 11) // previous mode. #define MSTATUS_MPP_M (3L << 11) #define MSTATUS_MPP_S (1L << 11) #define MSTATUS_MPP_U (0L << 11) -#define MSTATUS_MIE (1L << 3) +#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable. static inline uint64 r_mstatus() @@ -95,8 +95,8 @@ w_sie(uint64 x) // Machine-mode Interrupt Enable #define MIE_MEIE (1L << 11) // external -#define MIE_MTIE (1L << 7) // timer -#define MIE_MSIE (1L << 3) // software +#define MIE_MTIE (1L << 7) // timer +#define MIE_MSIE (1L << 3) // software static inline uint64 r_mie() { |