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| author | Jonathan Behrens <[email protected]> | 2021-08-30 16:27:52 -0400 |
|---|---|---|
| committer | Jonathan Behrens <[email protected]> | 2021-08-30 16:27:52 -0400 |
| commit | 9655f71758003f93294e82926783024a7e4bcdde (patch) | |
| tree | c7cc5a8d790f81d464433cfc45006bc5966d83ea /kernel/riscv.h | |
| parent | 6de0381d619f01777d84cbcd3affa96ad376c2e1 (diff) | |
| download | xv6-labs-9655f71758003f93294e82926783024a7e4bcdde.tar.gz xv6-labs-9655f71758003f93294e82926783024a7e4bcdde.tar.bz2 xv6-labs-9655f71758003f93294e82926783024a7e4bcdde.zip | |
Configure PMP at boot
Diffstat (limited to 'kernel/riscv.h')
| -rw-r--r-- | kernel/riscv.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index 0aec003..33b4335 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -181,6 +181,18 @@ w_mtvec(uint64 x) asm volatile("csrw mtvec, %0" : : "r" (x)); } +static inline void +w_pmpcfg0(uint64 x) +{ + asm volatile("csrw pmpcfg0, %0" : : "r" (x)); +} + +static inline void +w_pmpaddr0(uint64 x) +{ + asm volatile("csrw pmpaddr0, %0" : : "r" (x)); +} + // use riscv's sv39 page table scheme. #define SATP_SV39 (8L << 60) |