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authorMole Shang <[email protected]>2024-02-17 11:55:33 +0800
committerMole Shang <[email protected]>2024-02-17 12:22:07 +0800
commite8e0a7b4c97064eb5e9415726d7e38aaceccd3fd (patch)
treefb42ba5be7a8ae608b968266f62fd71fa889a89d /kernel/riscv.h
parenta6af72924b115c1177d18d9b1eaba56623e4248b (diff)
parentd85aec2689c4250d0384904bdc11aa618c726bec (diff)
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Merge branch 'thread' into fs
Conflicts: .gitignore Makefile conf/lab.mk kernel/param.h
Diffstat (limited to 'kernel/riscv.h')
-rw-r--r--kernel/riscv.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h
index 20a01db..af18972 100644
--- a/kernel/riscv.h
+++ b/kernel/riscv.h
@@ -327,6 +327,15 @@ sfence_vma()
asm volatile("sfence.vma zero, zero");
}
+// read the frame pointer of currently executing func
+static inline uint64
+r_fp()
+{
+ uint64 x;
+ asm volatile("mv %0, s0" : "=r" (x) );
+ return x;
+}
+
typedef uint64 pte_t;
typedef uint64 *pagetable_t; // 512 PTEs
@@ -343,6 +352,11 @@ typedef uint64 *pagetable_t; // 512 PTEs
#define PTE_W (1L << 2)
#define PTE_X (1L << 3)
#define PTE_U (1L << 4) // user can access
+#define PTE_A (1L << 6) // riscv access bit
+#define PTE_C (1L << 8) // RSW low bit, use it to mark whether a page is COW
+
+
+
// shift a physical address to the right place for a PTE.
#define PA2PTE(pa) ((((uint64)pa) >> 12) << 10)