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authorMole Shang <[email protected]>2024-02-14 20:46:23 +0800
committerMole Shang <[email protected]>2024-02-14 20:46:23 +0800
commitf98eeb30507040dc916b2a337818830954ee1d4a (patch)
treea741cb0bbd6be96d8084e72b4af895ac093a2b48 /kernel/riscv.h
parent0de5ac779602f562a038e5ad27163d85bc71638b (diff)
parent904885a96efd1dd0221585f67477f5a39bcce7f7 (diff)
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Merge branch 'net' into lock
Conflicts: .gitignore Makefile conf/lab.mk kernel/defs.h user/user.h
Diffstat (limited to 'kernel/riscv.h')
-rw-r--r--kernel/riscv.h19
1 files changed, 11 insertions, 8 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h
index adc3e38..af18972 100644
--- a/kernel/riscv.h
+++ b/kernel/riscv.h
@@ -295,14 +295,6 @@ r_sp()
return x;
}
-static inline uint64
-r_fp()
-{
- uint64 x;
- asm volatile("mv %0, s0" : "=r" (x) );
- return x;
-}
-
// read and write tp, the thread pointer, which xv6 uses to hold
// this core's hartid (core number), the index into cpus[].
static inline uint64
@@ -335,6 +327,15 @@ sfence_vma()
asm volatile("sfence.vma zero, zero");
}
+// read the frame pointer of currently executing func
+static inline uint64
+r_fp()
+{
+ uint64 x;
+ asm volatile("mv %0, s0" : "=r" (x) );
+ return x;
+}
+
typedef uint64 pte_t;
typedef uint64 *pagetable_t; // 512 PTEs
@@ -351,6 +352,8 @@ typedef uint64 *pagetable_t; // 512 PTEs
#define PTE_W (1L << 2)
#define PTE_X (1L << 3)
#define PTE_U (1L << 4) // user can access
+#define PTE_A (1L << 6) // riscv access bit
+#define PTE_C (1L << 8) // RSW low bit, use it to mark whether a page is COW