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| author | Mole Shang <[email protected]> | 2024-02-10 13:08:26 +0800 |
|---|---|---|
| committer | Mole Shang <[email protected]> | 2024-02-10 13:08:26 +0800 |
| commit | c9284cd93525436cc823258ab309c1b27eeec714 (patch) | |
| tree | 35782f7314100aa821823ee94cc5d28164af8000 /kernel/riscv.h | |
| parent | 283d5ab4c964ab525e45fcade06d6fd7e977c43e (diff) | |
| download | xv6-labs-c9284cd93525436cc823258ab309c1b27eeec714.tar.gz xv6-labs-c9284cd93525436cc823258ab309c1b27eeec714.tar.bz2 xv6-labs-c9284cd93525436cc823258ab309c1b27eeec714.zip | |
lab pgtbl: finishpgtbl
Diffstat (limited to 'kernel/riscv.h')
| -rw-r--r-- | kernel/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index 20a01db..33fa9ee 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -343,6 +343,7 @@ typedef uint64 *pagetable_t; // 512 PTEs #define PTE_W (1L << 2) #define PTE_X (1L << 3) #define PTE_U (1L << 4) // user can access +#define PTE_A (1L << 6) // riscv access bit // shift a physical address to the right place for a PTE. #define PA2PTE(pa) ((((uint64)pa) >> 12) << 10) |