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author | Jonathan Behrens <[email protected]> | 2021-08-30 16:27:52 -0400 |
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committer | Jonathan Behrens <[email protected]> | 2021-08-30 16:27:52 -0400 |
commit | 9655f71758003f93294e82926783024a7e4bcdde (patch) | |
tree | c7cc5a8d790f81d464433cfc45006bc5966d83ea /kernel | |
parent | 6de0381d619f01777d84cbcd3affa96ad376c2e1 (diff) | |
download | xv6-labs-9655f71758003f93294e82926783024a7e4bcdde.tar.gz xv6-labs-9655f71758003f93294e82926783024a7e4bcdde.tar.bz2 xv6-labs-9655f71758003f93294e82926783024a7e4bcdde.zip |
Configure PMP at boot
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/riscv.h | 12 | ||||
-rw-r--r-- | kernel/start.c | 5 |
2 files changed, 17 insertions, 0 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index 0aec003..33b4335 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -181,6 +181,18 @@ w_mtvec(uint64 x) asm volatile("csrw mtvec, %0" : : "r" (x)); } +static inline void +w_pmpcfg0(uint64 x) +{ + asm volatile("csrw pmpcfg0, %0" : : "r" (x)); +} + +static inline void +w_pmpaddr0(uint64 x) +{ + asm volatile("csrw pmpaddr0, %0" : : "r" (x)); +} + // use riscv's sv39 page table scheme. #define SATP_SV39 (8L << 60) diff --git a/kernel/start.c b/kernel/start.c index 1876680..938e837 100644 --- a/kernel/start.c +++ b/kernel/start.c @@ -38,6 +38,11 @@ start() w_mideleg(0xffff); w_sie(r_sie() | SIE_SEIE | SIE_STIE | SIE_SSIE); + // configure Physical Memory Protection to give supervisor mode + // access to all of physical memory. + w_pmpaddr0(0x3fffffffffffffull); + w_pmpcfg0(0xf); + // ask for clock interrupts. timerinit(); |