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author | rsc <rsc> | 2007-09-26 20:34:12 +0000 |
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committer | rsc <rsc> | 2007-09-26 20:34:12 +0000 |
commit | d5596cd61dd588781cde4b647075e39f07608c0a (patch) | |
tree | 406879201f72a3c9ef292e8ce2eb1cddc8131d79 /lapic.c | |
parent | 355073ea9e7528e45143efaa9631efcf159a2b68 (diff) | |
download | xv6-labs-d5596cd61dd588781cde4b647075e39f07608c0a.tar.gz xv6-labs-d5596cd61dd588781cde4b647075e39f07608c0a.tar.bz2 xv6-labs-d5596cd61dd588781cde4b647075e39f07608c0a.zip |
Apparently the initial interrupt count lapic[TICR]
must be set *after* initializing the lapic[TIMER] vector.
Doing this, we now get clock interrupts on cpu 1.
(No idea why we always got them on cpu 0.)
Don't write to TCCR - it is read-only.
Diffstat (limited to 'lapic.c')
-rw-r--r-- | lapic.c | 9 |
1 files changed, 3 insertions, 6 deletions
@@ -46,14 +46,11 @@ lapic_init(int c) // The timer repeatedly counts down at bus frequency // from lapic[TICR] and then issues an interrupt. - // Lapic[TCCR] is the current counter value. - // If xv6 cared more about precise timekeeping, the - // values of TICR and TCCR would be calibrated using - // an external time source. + // If xv6 cared more about precise timekeeping, + // TICR would be calibrated using an external time source. lapic[TDCR] = X1; - lapic[TICR] = 10000000; - lapic[TCCR] = 10000000; lapic[TIMER] = PERIODIC | (IRQ_OFFSET + IRQ_TIMER); + lapic[TICR] = 10000000; // Disable logical interrupt lines. lapic[LINT0] = MASKED; |