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authorrsc <rsc>2007-08-27 22:53:31 +0000
committerrsc <rsc>2007-08-27 22:53:31 +0000
commit99b11b6c64c17b94288c659e9398261e69a0cf75 (patch)
treec45cb8b500f14dbe69c3cba41dfa66766e589a63 /mp.h
parentb63bb0fd00cb34ed1d776e6836f5a2bb90de98c1 (diff)
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Simplify MP hardware code.
Mainly delete unused constants and code. Move mp_startthem to main.c as bootothers.
Diffstat (limited to 'mp.h')
-rw-r--r--mp.h84
1 files changed, 10 insertions, 74 deletions
diff --git a/mp.h b/mp.h
index b7c72d8..6453f65 100644
--- a/mp.h
+++ b/mp.h
@@ -1,4 +1,4 @@
-// See MultiProcessor Specification Version 1.[14].
+// See MultiProcessor Specification Version 1.[14]
struct mp { // floating pointer
uchar signature[4]; // "_MP_"
@@ -11,7 +11,7 @@ struct mp { // floating pointer
uchar reserved[3];
};
-struct mpctb { // configuration table header
+struct mpconf { // configuration table header
uchar signature[4]; // "PCMP"
ushort length; // total table length
uchar version; // [14]
@@ -26,22 +26,17 @@ struct mpctb { // configuration table header
uchar reserved;
};
-struct mppe { // processor table entry
+struct mpproc { // processor table entry
uchar type; // entry type (0)
uchar apicid; // local APIC id
uchar version; // local APIC verison
uchar flags; // CPU flags
+ #define MPBOOT 0x02 // This proc is the bootstrap processor.
uchar signature[4]; // CPU signature
uint feature; // feature flags from CPUID instruction
uchar reserved[8];
};
-struct mpbe { // bus table entry
- uchar type; // entry type (1)
- uchar busno; // bus id
- char string[6]; // bus type string
-};
-
struct mpioapic { // I/O APIC table entry
uchar type; // entry type (2)
uchar apicno; // I/O APIC id
@@ -50,69 +45,10 @@ struct mpioapic { // I/O APIC table entry
uint *addr; // I/O APIC address
};
-struct mpie { // interrupt table entry
- uchar type; // entry type ([34])
- uchar intr; // interrupt type
- ushort flags; // interrupt flag
- uchar busno; // source bus id
- uchar irq; // source bus irq
- uchar apicno; // destination APIC id
- uchar intin; // destination APIC [L]INTIN#
-};
-
-enum { // table entry types
- MPPROCESSOR = 0x00, // one entry per processor
- MPBUS = 0x01, // one entry per bus
- MPIOAPIC = 0x02, // one entry per I/O APIC
- MPIOINTR = 0x03, // one entry per bus interrupt source
- MPLINTR = 0x04, // one entry per system interrupt source
-
- MPSASM = 0x80,
- MPHIERARCHY = 0x81,
- MPCBASM = 0x82,
-
- // PCMPprocessor and PCMPioapic flags
- MPEN = 0x01, // enabled
- MPBP = 0x02, // bootstrap processor
-
- // PCMPiointr and PCMPlintr flags
- MPPOMASK = 0x03, // polarity conforms to bus specs
- MPHIGH = 0x01, // active high
- MPLOW = 0x03, // active low
- MPELMASK = 0x0C, // trigger mode of APIC input signals
- MPEDGE = 0x04, // edge-triggered
- MPLEVEL = 0x0C, // level-triggered
-
- // PCMPiointr and PCMPlintr interrupt type
- MPINT = 0x00, // vectored interrupt from APIC Rdt
- MPNMI = 0x01, // non-maskable interrupt
- MPSMI = 0x02, // system management interrupt
- MPExtINT = 0x03, // vectored interrupt from external PIC
-};
-
-// Common bits for
-// I/O APIC Redirection Table Entry;
-// Local APIC Local Interrupt Vector Table;
-// Local APIC Inter-Processor Interrupt;
-// Local APIC Timer Vector Table.
-enum {
- APIC_FIXED = 0x00000000, // [10:8] Delivery Mode
- APIC_LOWEST = 0x00000100, // Lowest priority
- APIC_SMI = 0x00000200, // System Management Interrupt
- APIC_RR = 0x00000300, // Remote Read
- APIC_NMI = 0x00000400,
- APIC_INIT = 0x00000500, // INIT/RESET
- APIC_STARTUP = 0x00000600, // Startup IPI
- APIC_EXTINT = 0x00000700,
-
- APIC_PHYSICAL = 0x00000000, // [11] Destination Mode (RW)
- APIC_LOGICAL = 0x00000800,
+// Table entry types
+#define MPPROC 0x00 // One per processor
+#define MPBUS 0x01 // One per bus
+#define MPIOAPIC 0x02 // One per I/O APIC
+#define MPIOINTR 0x03 // One per bus interrupt source
+#define MPLINTR 0x04 // One per system interrupt source
- APIC_DELIVS = 0x00001000, // [12] Delivery Status (RO)
- APIC_HIGH = 0x00000000, // [13] Interrupt Input Pin Polarity (RW)
- APIC_LOW = 0x00002000,
- APIC_REMOTEIRR = 0x00004000, // [14] Remote IRR (RO)
- APIC_EDGE = 0x00000000, // [15] Trigger Mode (RW)
- APIC_LEVEL = 0x00008000,
- APIC_IMASK = 0x00010000, // [16] Interrupt Mask
-};