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author | rsc <rsc> | 2006-09-06 17:50:20 +0000 |
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committer | rsc <rsc> | 2006-09-06 17:50:20 +0000 |
commit | f552738889f56586728d1b5d2a63cde0cf124929 (patch) | |
tree | e91c4b41699f12d686383556fbbe67baa41d9575 /picirq.c | |
parent | 9e9bcaf143bf8507e947f9934371744c3d50a8ea (diff) | |
download | xv6-labs-f552738889f56586728d1b5d2a63cde0cf124929.tar.gz xv6-labs-f552738889f56586728d1b5d2a63cde0cf124929.tar.bz2 xv6-labs-f552738889f56586728d1b5d2a63cde0cf124929.zip |
no /* */ comments
Diffstat (limited to 'picirq.c')
-rw-r--r-- | picirq.c | 10 |
1 files changed, 5 insertions, 5 deletions
@@ -22,7 +22,7 @@ irq_setmask_8259A(ushort mask) outb(IO_PIC2+1, (char)(mask >> 8)); } -/* Initialize the 8259A interrupt controllers. */ +// Initialize the 8259A interrupt controllers. void pic_init(void) { @@ -67,11 +67,11 @@ pic_init(void) // ef: 0x = NOP, 10 = clear specific mask, 11 = set specific mask // p: 0 = no polling, 1 = polling mode // rs: 0x = NOP, 10 = read IRR, 11 = read ISR - outb(IO_PIC1, 0x68); /* clear specific mask */ - outb(IO_PIC1, 0x0a); /* read IRR by default */ + outb(IO_PIC1, 0x68); // clear specific mask + outb(IO_PIC1, 0x0a); // read IRR by default - outb(IO_PIC2, 0x68); /* OCW3 */ - outb(IO_PIC2, 0x0a); /* OCW3 */ + outb(IO_PIC2, 0x68); // OCW3 + outb(IO_PIC2, 0x0a); // OCW3 if(irq_mask_8259A != 0xFFFF) irq_setmask_8259A(irq_mask_8259A); |