summaryrefslogtreecommitdiff
path: root/riscv.h
diff options
context:
space:
mode:
authorRobert Morris <[email protected]>2019-06-04 10:43:45 -0400
committerRobert Morris <[email protected]>2019-06-04 10:43:45 -0400
commit0e131b226336808c135795f5b9d7defc5a58b2ae (patch)
tree226cf0c8f1043d99175aee8835baf570cdf662e6 /riscv.h
parentb78894f34ebbceb23bcf36ff820fefb942b54ccf (diff)
downloadxv6-labs-0e131b226336808c135795f5b9d7defc5a58b2ae.tar.gz
xv6-labs-0e131b226336808c135795f5b9d7defc5a58b2ae.tar.bz2
xv6-labs-0e131b226336808c135795f5b9d7defc5a58b2ae.zip
fix a problem with end. make uartputc() wait until h/w is ready.
Diffstat (limited to 'riscv.h')
-rw-r--r--riscv.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/riscv.h b/riscv.h
index 6ecee84..d59503c 100644
--- a/riscv.h
+++ b/riscv.h
@@ -132,6 +132,14 @@ w_stvec(uint64 x)
asm("csrw stvec, %0" : : "r" (x));
}
+static inline uint64
+r_stvec()
+{
+ uint64 x;
+ asm("csrr %0, stvec" : "=r" (x) );
+ return x;
+}
+
// use riscv's sv39 page table scheme.
#define SATP_SV39 (8L << 60)
@@ -201,6 +209,14 @@ intr_get()
return (x & SSTATUS_SIE) != 0;
}
+static inline uint64
+r_sp()
+{
+ uint64 x;
+ asm("mv %0, sp" : "=r" (x) );
+ return x;
+}
+
#define PGSIZE 4096 // bytes per page
#define PGSHIFT 12 // bits of offset within a page