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author | Robert Morris <[email protected]> | 2019-06-05 11:42:03 -0400 |
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committer | Robert Morris <[email protected]> | 2019-06-05 11:42:03 -0400 |
commit | f1a727b971a59bab6025b4c4111342c27356ca40 (patch) | |
tree | d22d52c613bfc003e6fb75b5d137aeff9d954201 /riscv.h | |
parent | ec3d3a1fceee437c640f9c5c05fc517edfb1899e (diff) | |
download | xv6-labs-f1a727b971a59bab6025b4c4111342c27356ca40.tar.gz xv6-labs-f1a727b971a59bab6025b4c4111342c27356ca40.tar.bz2 xv6-labs-f1a727b971a59bab6025b4c4111342c27356ca40.zip |
start at support for multiple CPUs
Diffstat (limited to 'riscv.h')
-rw-r--r-- | riscv.h | 25 |
1 files changed, 25 insertions, 0 deletions
@@ -1,3 +1,12 @@ +// which hart (core) is this? +static inline uint64 +r_mhartid() +{ + uint64 x; + asm("csrr %0, mhartid" : "=r" (x) ); + return x; +} + // Machine Status Register, mstatus #define MSTATUS_MPP_MASK (3L << 11) @@ -279,6 +288,22 @@ r_sp() return x; } +// read and write tp, the thread pointer, which holds +// this core's hartid (core number), the index into cpus[]. +static inline uint64 +r_tp() +{ + uint64 x; + asm("mv %0, tp" : "=r" (x) ); + return x; +} + +static inline void +w_tp(uint64 x) +{ + asm("mv tp, %0" : : "r" (x)); +} + #define PGSIZE 4096 // bytes per page #define PGSHIFT 12 // bits of offset within a page |