diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | riscv.h | 66 | ||||
| -rw-r--r-- | start.c | 2 |
3 files changed, 35 insertions, 35 deletions
@@ -50,7 +50,7 @@ OBJCOPY = $(TOOLPREFIX)objcopy OBJDUMP = $(TOOLPREFIX)objdump # CFLAGS = -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -MD -ggdb -Werror -fno-omit-frame-pointer -O -CFLAGS = -Wall -Werror +CFLAGS = -Wall -Werror -O CFLAGS += -mcmodel=medany CFLAGS += -ffreestanding -fno-common -nostdlib -mno-relax CFLAGS += $(shell $(CC) -fno-stack-protector -E -x c /dev/null >/dev/null 2>&1 && echo -fno-stack-protector) @@ -3,7 +3,7 @@ static inline uint64 r_mhartid() { uint64 x; - asm("csrr %0, mhartid" : "=r" (x) ); + asm volatile("csrr %0, mhartid" : "=r" (x) ); return x; } @@ -19,14 +19,14 @@ static inline uint64 r_mstatus() { uint64 x; - asm("csrr %0, mstatus" : "=r" (x) ); + asm volatile("csrr %0, mstatus" : "=r" (x) ); return x; } static inline void w_mstatus(uint64 x) { - asm("csrw mstatus, %0" : : "r" (x)); + asm volatile("csrw mstatus, %0" : : "r" (x)); } // machine exception program counter, holds the @@ -35,7 +35,7 @@ w_mstatus(uint64 x) static inline void w_mepc(uint64 x) { - asm("csrw mepc, %0" : : "r" (x)); + asm volatile("csrw mepc, %0" : : "r" (x)); } // Supervisor Status Register, sstatus @@ -50,14 +50,14 @@ static inline uint64 r_sstatus() { uint64 x; - asm("csrr %0, sstatus" : "=r" (x) ); + asm volatile("csrr %0, sstatus" : "=r" (x) ); return x; } static inline void w_sstatus(uint64 x) { - asm("csrw sstatus, %0" : : "r" (x)); + asm volatile("csrw sstatus, %0" : : "r" (x)); } // Supervisor Interrupt Pending @@ -65,14 +65,14 @@ static inline uint64 r_sip() { uint64 x; - asm("csrr %0, sip" : "=r" (x) ); + asm volatile("csrr %0, sip" : "=r" (x) ); return x; } static inline void w_sip(uint64 x) { - asm("csrw sip, %0" : : "r" (x)); + asm volatile("csrw sip, %0" : : "r" (x)); } // Supervisor Interrupt Enable @@ -83,14 +83,14 @@ static inline uint64 r_sie() { uint64 x; - asm("csrr %0, sie" : "=r" (x) ); + asm volatile("csrr %0, sie" : "=r" (x) ); return x; } static inline void w_sie(uint64 x) { - asm("csrw sie, %0" : : "r" (x)); + asm volatile("csrw sie, %0" : : "r" (x)); } // Machine-mode Interrupt Enable @@ -101,14 +101,14 @@ static inline uint64 r_mie() { uint64 x; - asm("csrr %0, mie" : "=r" (x) ); + asm volatile("csrr %0, mie" : "=r" (x) ); return x; } static inline void w_mie(uint64 x) { - asm("csrw mie, %0" : : "r" (x)); + asm volatile("csrw mie, %0" : : "r" (x)); } // machine exception program counter, holds the @@ -117,14 +117,14 @@ w_mie(uint64 x) static inline void w_sepc(uint64 x) { - asm("csrw sepc, %0" : : "r" (x)); + asm volatile("csrw sepc, %0" : : "r" (x)); } static inline uint64 r_sepc() { uint64 x; - asm("csrr %0, sepc" : "=r" (x) ); + asm volatile("csrr %0, sepc" : "=r" (x) ); return x; } @@ -133,14 +133,14 @@ static inline uint64 r_medeleg() { uint64 x; - asm("csrr %0, medeleg" : "=r" (x) ); + asm volatile("csrr %0, medeleg" : "=r" (x) ); return x; } static inline void w_medeleg(uint64 x) { - asm("csrw medeleg, %0" : : "r" (x)); + asm volatile("csrw medeleg, %0" : : "r" (x)); } // Machine Interrupt Delegation @@ -148,14 +148,14 @@ static inline uint64 r_mideleg() { uint64 x; - asm("csrr %0, mideleg" : "=r" (x) ); + asm volatile("csrr %0, mideleg" : "=r" (x) ); return x; } static inline void w_mideleg(uint64 x) { - asm("csrw mideleg, %0" : : "r" (x)); + asm volatile("csrw mideleg, %0" : : "r" (x)); } // Supervisor Trap-Vector Base Address @@ -163,14 +163,14 @@ w_mideleg(uint64 x) static inline void w_stvec(uint64 x) { - asm("csrw stvec, %0" : : "r" (x)); + asm volatile("csrw stvec, %0" : : "r" (x)); } static inline uint64 r_stvec() { uint64 x; - asm("csrr %0, stvec" : "=r" (x) ); + asm volatile("csrr %0, stvec" : "=r" (x) ); return x; } @@ -178,7 +178,7 @@ r_stvec() static inline void w_mtvec(uint64 x) { - asm("csrw mtvec, %0" : : "r" (x)); + asm volatile("csrw mtvec, %0" : : "r" (x)); } // use riscv's sv39 page table scheme. @@ -191,14 +191,14 @@ w_mtvec(uint64 x) static inline void w_satp(uint64 x) { - asm("csrw satp, %0" : : "r" (x)); + asm volatile("csrw satp, %0" : : "r" (x)); } static inline uint64 r_satp() { uint64 x; - asm("csrr %0, satp" : "=r" (x) ); + asm volatile("csrr %0, satp" : "=r" (x) ); return x; } @@ -206,13 +206,13 @@ r_satp() static inline void w_sscratch(uint64 x) { - asm("csrw sscratch, %0" : : "r" (x)); + asm volatile("csrw sscratch, %0" : : "r" (x)); } static inline void w_mscratch(uint64 x) { - asm("csrw mscratch, %0" : : "r" (x)); + asm volatile("csrw mscratch, %0" : : "r" (x)); } // Supervisor Trap Cause @@ -220,7 +220,7 @@ static inline uint64 r_scause() { uint64 x; - asm("csrr %0, scause" : "=r" (x) ); + asm volatile("csrr %0, scause" : "=r" (x) ); return x; } @@ -229,7 +229,7 @@ static inline uint64 r_stval() { uint64 x; - asm("csrr %0, stval" : "=r" (x) ); + asm volatile("csrr %0, stval" : "=r" (x) ); return x; } @@ -237,14 +237,14 @@ r_stval() static inline void w_mcounteren(uint64 x) { - asm("csrw mcounteren, %0" : : "r" (x)); + asm volatile("csrw mcounteren, %0" : : "r" (x)); } static inline uint64 r_mcounteren() { uint64 x; - asm("csrr %0, mcounteren" : "=r" (x) ); + asm volatile("csrr %0, mcounteren" : "=r" (x) ); return x; } @@ -253,7 +253,7 @@ static inline uint64 r_time() { uint64 x; - asm("csrr %0, time" : "=r" (x) ); + asm volatile("csrr %0, time" : "=r" (x) ); return x; } @@ -284,7 +284,7 @@ static inline uint64 r_sp() { uint64 x; - asm("mv %0, sp" : "=r" (x) ); + asm volatile("mv %0, sp" : "=r" (x) ); return x; } @@ -294,14 +294,14 @@ static inline uint64 r_tp() { uint64 x; - asm("mv %0, tp" : "=r" (x) ); + asm volatile("mv %0, tp" : "=r" (x) ); return x; } static inline void w_tp(uint64 x) { - asm("mv tp, %0" : : "r" (x)); + asm volatile("mv tp, %0" : : "r" (x)); } #define PGSIZE 4096 // bytes per page @@ -52,5 +52,5 @@ mstart() w_tp(id); // call main() in supervisor mode. - asm("mret"); + asm volatile("mret"); } |