summaryrefslogtreecommitdiff
path: root/lapic.c
AgeCommit message (Collapse)AuthorFilesLines
2019-06-05start at support for multiple CPUsRobert Morris1-229/+0
2018-08-30xFrans Kaashoek1-3/+6
2017-08-29fix runoff complaints about pagination and long linesRobert Morris1-1/+1
2017-02-01A tiny bit of clean up (e.g., move code searching cpu array from lapic.c intoFrans Kaashoek1-13/+2
mycpu() in proc.c.
2017-02-01Eliminate code for gs trick to track per-cpu state. We rely on lapiccpunum()Frans Kaashoek1-12/+2
to find a per-cpu id with which we locate a cpu's cpu struct.
2017-01-31Start of an experiment to remove the use of gs for cpu local variables.Frans Kaashoek1-3/+3
2016-09-02APIC IDs may not be consecutive and start from zero, so we cannot really use itFrans Kaashoek1-3/+13
as a direct index into cpus. Record apicid in struct cpu and have cpunum() look for it. Replace cpu->id with cpunum() everywhere, and replace cpu->id with cpu->apicid. Thanks to Xi Wang.
2016-08-19xFrans Kaashoek1-6/+6
2016-08-18Coding style (thanks to phf).Frans Kaashoek1-5/+5
2014-09-12cmosgetdate() for system-call homeworkCody Cutler1-3/+68
the day of reckoning has come for the debug port "Shutdown" hack. instead of mucking with ACPI or using a new hack, the student will now write sys_date() using the cmosgetdate() helper.
2012-08-22Remove unused argument from lapicinit (thanks to Peter Froehlich)Frans Kaashoek1-1/+1
2011-09-02Fix weird pagebreak bugAustin Clements1-1/+1
2011-08-16Clean up memlayout.hFrans Kaashoek1-1/+2
Get rid of last instances of linear address and "la" Get ready for detecting physical memory dynamically
2011-08-15Avoid "boot" in xv6Frans Kaashoek1-2/+2
2011-08-11Make AP processors boot using bootpgdirFrans Kaashoek1-1/+0
Remove device mapping from bootpgdir Remove unnecessary vmenable Set CPUS back to 2 in Makefile Passes all usertests
2011-08-09One more low addressFrans Kaashoek1-1/+3
2010-07-28kill TLB shoot down codeFrans Kaashoek1-38/+0
2010-07-23Checkpoint page-table version for SMPFrans Kaashoek1-0/+40
Includes code for TLB shootdown (which actually seems unnecessary for xv6)
2010-07-02Initial version of single-cpu xv6 with page tablesFrans Kaashoek1-0/+1
2009-09-02lapic: disable microdelay because it makes Bochs slowRuss Cox1-4/+0
2009-08-30assorted fixes:Russ Cox1-1/+1
* rename c/cp to cpu/proc * rename cpu.context to cpu.scheduler * fix some comments * formatting for printout
2009-07-11trap cleanupRuss Cox1-3/+3
IRQ_OFFSET -> T_IRQ0 (a trap number not an IRQ number) T_SYSCALL 0x30 -> 0x40 (move out of IRQ range)
2009-05-31tab policersc1-1/+1
2009-05-31Some proc cleanup, moving some of copyproc into allocproc.rsc1-1/+1
Also, an experiment: use "thread-local" storage for c and cp instead of the #define macro for curproc[cpu()].
2009-03-08be consistent: no underscores in function namesrsc1-5/+5
2008-10-12minor cleanupkolya1-2/+2
2007-11-28More complete lapic startup (thanks Silas)rsc1-8/+26
2007-09-27cleanerrsc1-10/+2
2007-09-27better lapic writes, suggested by cliffrsc1-19/+26
2007-09-27kernel SMP interruptibility fixes.rsc1-0/+22
Last year, right before I sent xv6 to the printer, I changed the SETGATE calls so that interrupts would be disabled on entry to interrupt handlers, and I added the nlock++ / nlock-- in trap() so that interrupts would stay disabled while the hw handlers (but not the syscall handler) did their work. I did this because the kernel was otherwise causing Bochs to triple-fault in SMP mode, and time was short. Robert observed yesterday that something was keeping the SMP preemption user test from working. It turned out that when I simplified the lapic code I swapped the order of two register writes that I didn't realize were order dependent. I fixed that and then since I had everything paged in kept going and tried to figure out why you can't leave interrupts on during interrupt handlers. There are a few issues. First, there must be some way to keep interrupts from "stacking up" and overflowing the stack. Keeping interrupts off the whole time solves this problem -- even if the clock tick handler runs long enough that the next clock tick is waiting when it finishes, keeping interrupts off means that the handler runs all the way through the "iret" before the next handler begins. This is not really a problem unless you are putting too many prints in trap -- if the OS is doing its job right, the handlers should run quickly and not stack up. Second, if xv6 had page faults, then it would be important to keep interrupts disabled between the start of the interrupt and the time that cr2 was read, to avoid a scenario like: p1 page faults [cr2 set to faulting address] p1 starts executing trapasm.S clock interrupt, p1 preempted, p2 starts executing p2 page faults [cr2 set to another faulting address] p2 starts, finishes fault handler p1 rescheduled, reads cr2, sees wrong fault address Alternately p1 could be rescheduled on the other cpu, in which case it would still see the wrong cr2. That said, I think cr2 is the only interrupt state that isn't pushed onto the interrupt stack atomically at fault time, and xv6 doesn't care. (This isn't entirely hypothetical -- I debugged this problem on Plan 9.) Third, and this is the big one, it is not safe to call cpu() unless interrupts are disabled. If interrupts are enabled then there is no guarantee that, between the time cpu() looks up the cpu id and the time that it the result gets used, the process has not been rescheduled to the other cpu. For example, the very commonly-used expression curproc[cpu()] (aka the macro cp) can end up referring to the wrong proc: the code stores the result of cpu() in %eax, gets rescheduled to the other cpu at just the wrong instant, and then reads curproc[%eax]. We use curproc[cpu()] to get the current process a LOT. In that particular case, if we arranged for the current curproc entry to be addressed by %fs:0 and just use a different %fs on each CPU, then we could safely get at curproc even with interrupts disabled, since the read of %fs would be atomic with the read of %fs:0. Alternately, we could have a curproc() function that disables interrupts while computing curproc[cpu()]. I've done that last one. Even in the current kernel, with interrupts off on entry to trap, interrupts are enabled inside release if there are no locks held. Also, the scheduler's idle loop must be interruptible at times so that the clock and disk interrupts (which might make processes runnable) can be handled. In addition to the rampant use of curproc[cpu()], this little snippet from acquire is wrong on smp: if(cpus[cpu()].nlock == 0) cli(); cpus[cpu()].nlock++; because if interrupts are off then we might call cpu(), get rescheduled to a different cpu, look at cpus[oldcpu].nlock, and wrongly decide not to disable interrupts on the new cpu. The fix is to always call cli(). But this is wrong too: if(holding(lock)) panic("acquire"); cli(); cpus[cpu()].nlock++; because holding looks at cpu(). The fix is: cli(); if(holding(lock)) panic("acquire"); cpus[cpu()].nlock++; I've done that, and I changed cpu() to complain the first time it gets called with interrupts disabled. (It gets called too much to complain every time.) I added new functions splhi and spllo that are like acquire and release but without the locking: void splhi(void) { cli(); cpus[cpu()].nsplhi++; } void spllo(void) { if(--cpus[cpu()].nsplhi == 0) sti(); } and I've used those to protect other sections of code that refer to cpu() when interrupts would otherwise be disabled (basically just curproc and setupsegs). I also use them in acquire/release and got rid of nlock. I'm not thrilled with the names, but I think the concept -- a counted cli/sti -- is sound. Having them also replaces the nlock++/nlock-- in trap.c and main.c, which is nice. Final note: it's still not safe to enable interrupts in the middle of trap() between lapic_eoi and returning to user space. I don't understand why, but we get a fault on pop %es because 0x10 is a bad segment descriptor (!) and then the fault faults trying to go into a new interrupt because 0x8 is a bad segment descriptor too! Triple fault. I haven't debugged this yet.
2007-09-26comment bochs nonsensersc1-0/+2
2007-09-26Apparently the initial interrupt count lapic[TICR]rsc1-6/+3
must be set *after* initializing the lapic[TIMER] vector. Doing this, we now get clock interrupts on cpu 1. (No idea why we always got them on cpu 0.) Don't write to TCCR - it is read-only.
2007-08-27delete unnecessary #include linesrsc1-5/+0
2007-08-27Simplify MP hardware code.rsc1-91/+62
Mainly delete unused constants and code. Move mp_startthem to main.c as bootothers.
2007-08-27Clean up lapic code.rsc1-168/+120
One initialization function now, not three. Use #defines instead of enums (consistent with other code, but sigh). Still boots in Bochs in SMP mode.
2007-08-10replace bogus loops with slightly less bogus loops.rsc1-5/+3
2006-09-08formatting nitsrsc1-7/+7
2006-09-08consistency.kaashoek1-8/+9
2006-09-07run without lapic and ioapic, if they are not presentkaashoek1-10/+23
if no lapic available, use 8253pit for clock now xv6 runs both on qemu (uniprocessor) and bochs (uniprocessor and MP)
2006-09-06wrap long linesrsc1-10/+16
2006-09-06more tabs go awayrsc1-62/+62
2006-09-06no /* */ commentsrsc1-71/+69
2006-09-06standardize various * conventionsrsc1-7/+7
2006-09-04a few nitskaashoek1-1/+0
2006-09-03centralize creditskaashoek1-5/+0
2006-08-29prune unneeded panics and debug outputrtm1-6/+1
2006-08-23i/o redirection in shkaashoek1-1/+1
better parsing of sh commands (copied from jos sh) cat: read from 1 if no args sbrk system call, but untested getpid system call moved locks in keyboard intr, but why do we get intr w. null characters from keyboard?
2006-08-08fix race in holding() check in acquire()rtm1-5/+6
give cpu1 a TSS and gdt for when it enters scheduler() and a pseudo proc[] entry for each cpu cpu0 waits for each other cpu to start up read() for files
2006-08-04better interrupt plan---this one appears to workkaashoek1-0/+6
ioapic
2006-07-20uint32_t -> uint &crtm1-3/+3