From 1ed40716eb54e371df9d1814b9129666b3fe4f09 Mon Sep 17 00:00:00 2001
From: Sanjit Bhat <sanjit.bhat@gmail.com>
Date: Wed, 25 Oct 2023 19:42:59 -0400
Subject: release lab net

---
 kernel/plic.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'kernel/plic.c')

diff --git a/kernel/plic.c b/kernel/plic.c
index 4175db9..5c9d96a 100644
--- a/kernel/plic.c
+++ b/kernel/plic.c
@@ -14,6 +14,13 @@ plicinit(void)
   // set desired IRQ priorities non-zero (otherwise disabled).
   *(uint32*)(PLIC + UART0_IRQ*4) = 1;
   *(uint32*)(PLIC + VIRTIO0_IRQ*4) = 1;
+  
+#ifdef LAB_NET
+  // PCIE IRQs are 32 to 35
+  for(int irq = 1; irq < 0x35; irq++){
+    *(uint32*)(PLIC + irq*4) = 1;
+  }
+#endif  
 }
 
 void
@@ -25,6 +32,11 @@ plicinithart(void)
   // for the uart and virtio disk.
   *(uint32*)PLIC_SENABLE(hart) = (1 << UART0_IRQ) | (1 << VIRTIO0_IRQ);
 
+#ifdef LAB_NET
+  // hack to get at next 32 IRQs for e1000
+  *(uint32*)(PLIC_SENABLE(hart)+4) = 0xffffffff;
+#endif
+  
   // set this hart's S-mode priority threshold to 0.
   *(uint32*)PLIC_SPRIORITY(hart) = 0;
 }
-- 
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