#include "types.h" #include "param.h" #include "memlayout.h" #include "riscv.h" #include "defs.h" // // the riscv Platform Level Interrupt Controller (PLIC). // void plicinit(void) { // set desired IRQ priorities non-zero (otherwise disabled). *(uint32*)(PLIC + UART0_IRQ*4) = 1; *(uint32*)(PLIC + VIRTIO0_IRQ*4) = 1; #ifdef LAB_NET // PCIE IRQs are 32 to 35 for(int irq = 1; irq < 0x35; irq++){ *(uint32*)(PLIC + irq*4) = 1; } #endif } void plicinithart(void) { int hart = cpuid(); // set enable bits for this hart's S-mode // for the uart and virtio disk. *(uint32*)PLIC_SENABLE(hart) = (1 << UART0_IRQ) | (1 << VIRTIO0_IRQ); #ifdef LAB_NET // hack to get at next 32 IRQs for e1000 *(uint32*)(PLIC_SENABLE(hart)+4) = 0xffffffff; #endif // set this hart's S-mode priority threshold to 0. *(uint32*)PLIC_SPRIORITY(hart) = 0; } // ask the PLIC what interrupt we should serve. int plic_claim(void) { int hart = cpuid(); int irq = *(uint32*)PLIC_SCLAIM(hart); return irq; } // tell the PLIC we've served this IRQ. void plic_complete(int irq) { int hart = cpuid(); *(uint32*)PLIC_SCLAIM(hart) = irq; }